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Macros</h2></td></tr>
<tr class="memitem:gacd33f4473000380669cb9147110cac62"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__usb__v5__0.html#gacd33f4473000380669cb9147110cac62">XUsb_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;XUsb_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="separator:gacd33f4473000380669cb9147110cac62"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7598429f7ba0bb7f052da4eb95d0908b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__usb__v5__0.html#ga7598429f7ba0bb7f052da4eb95d0908b">XUsb_WriteReg</a>(BaseAddress,  RegOffset,  RegisterValue)&#160;&#160;&#160;XUsb_Out32((BaseAddress) + (RegOffset), (RegisterValue))</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Register Map</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register offsets for the USB device. </p>
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<tr><td colspan="2"><div class="groupHeader">Address Register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Control Register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Status Register and Interrupt Enable Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p><b> Status Register </b></p>
<p>This register holds the status flags for the USB device.</p>
<p><b> Interrupt Enable Register </b></p>
<p>This register is used to enable interrupt sources for the USB device. Writing a '1' to a bit in this register enables the corresponding Interrupt. Writing a '0' to a bit in this register disables the corresponding Interrupt.</p>
<p>Both these registers have the same bit definitions and are only defined once. </p>
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<tr><td colspan="2"><div class="groupHeader">Frame Number Register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Buffer Ready Register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Test Mode Register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Error Counter Register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">ULPI PHY Access Register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Endpoint Configuration Space offsets</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Endpoint Configuration Status Register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">DMA Reset/Control and Status register bits</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">HSIC PHY Registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>User need not program HSIC PHY registers for normal operation.</p>
<p>These are provided to test the PHY access only. </p>
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